1. Technical Field
Example embodiments relate to a non-volatile memory device and a method of manufacturing the non-volatile memory device such as, a non-volatile memory device including a charge trapping layer.
2. Description of the Related Art
Semiconductor memory devices, in general, may be classified as either volatile or non-volatile semiconductor memory devices. Volatile semiconductor memory devices such as dynamic random access memory (DRAM) devices and/or static random access memory (SRAM) devices may have a relatively high response speed. However, volatile semiconductor memory devices may lose stored data when power is lost. Although non-volatile semiconductor memory devices, such as electrically erasable programmable read only memory (EEPROM) devices and/or flash memory devices, may have a relatively slow response speed, such devices may maintain stored data even when power is lost.
In EEPROM devices, data may be electronically stored, e.g., programmed, or erased through a Fowler-Nordheim (F-N) tunneling mechanism and/or a channel hot electron injection mechanism. The flash memory device may be classified as either a floating gate type or a charge trap type, such as silicon oxide nitride oxide semiconductor (SONOS) type devices and/or metal oxide nitride oxide semiconductor (MONOS) type devices.
A SONOS or MONOS type non-volatile memory device may include a tunnel insulating layer formed on a channel region of a semiconductor substrate, a charge trapping layer for trapping electrons from the channel region, a blocking layer formed on the charge trapping layer, a gate electrode formed on the blocking layer, spacers formed on sidewalls of the gate electrode and/or source/drain regions formed at surface portions of the semiconductor substrate adjacent to the channel region.
FIG. 1 is a cross-sectional view taken along a word line of a conventional non-volatile memory device, and FIG. 2 is a cross-sectional view taken in a direction substantially perpendicular to the word line of the conventional non-volatile memory device.
Referring to FIGS. 1 and 2, a conventional non-volatile memory device 1 may include field insulating patterns 12 formed at surface portions of a semiconductor substrate 10 to define active regions 10a. 
The conventional non-volatile memory device 1 may further include a plurality of memory cells 1a and 1b. Word lines 20 may extend on the semiconductor substrate 10 in a direction substantially perpendicular to an extending direction of the active regions 10a. A tunnel insulating layer 14, a charge trapping layer 16 and a blocking layer 18 may be disposed between the semiconductor substrate 10 and each of the word lines 20. That is, a plurality of gate structures 22 may be disposed on the semiconductor substrate 10, which may include the tunnel insulating layer 14, the charge trapping layer 16, the blocking layer 18 and the word line 20, and may extend in a word line direction. Source/drain regions 24 may be formed at surface portions of the active regions 10a adjacent to the gate structures 22, and channel regions 10b may be positioned underneath the gate structures 22.
The memory cells 1a and 1b may be disposed on the active regions 10a, and the memory cells 1a and 1b may be programmed or erased by applying a programming or erasing voltage to the word line 20 serving as gate electrodes. When a programming voltage is applied to the word line 20, electrons are trapped in trap sites of the charge trapping layer 16 from the channel region 10b through the tunnel insulating layer 14, and thus one bit of data may be stored in the charge trapping layer 14. When an erasing voltage is applied to the word line 20, electrons may be discharged from the charge trapping layer 16 into the channel region 10b through the tunnel insulating layer 14, and thus the stored data in the charge trapping layer 14 may be erased.
Each of the memory cells 1a and 1b may be used as a multi-level cell (MLC) to increase the data storage capacity of the non-volatile memory device 1. When either of the memory cells 1a and 1b is used as the MLC, it may be desirable to form the charge trapping layer 16 using a material having a high trap density. The high trap density of the charge trapping layer 16 may cause lateral charge diffusion in the charge trapping layer 16. For example, when a memory cell 1a is programmed and an adjacent cell 1b is erased, electrons 26 trapped in the charge trapping layer 16 may move from the programmed memory cell 1a towards the erased memory cell 1b, as shown in FIG. 1.
As a result of the migration of electrons, the lateral charge diffusion in the charge trapping layer 16 may deteriorate data retention performance and also deteriorate the reliability of the non-volatile memory device 1. When a reading voltage is applied to the word line 20 to read the data stored in the programmed memory cell 1a, lateral charge diffusion may be accelerated.